- HELP
EVDAA
THIS PROGRAM CHECKS THE FUNCTIONALITY OF THE DZ-11, PROVIDING
ERROR MESSAGES TO AID IN THE REPAIR OF THE DEVICE. THE DIAGNOSTIC
USES THE INTERNAL LOOPBACK MODE TO CHECK MOST OF THE CIRCUITRY OF
THE DEVICE. THERE IS A SECTION (H327) PROVIDED TO CHECK THE MODEM
CONTROL FEATURE OF THE M7819 (EIA) MODULE. THERE IS ALSO A SECTION
(H3190) PROVIDED TO ALLOW USE OF THE H3190 TURNAROUND CONNECTOR FOR
THE M7814 (20MA) MODULE.
ALL 20MA LINES SHOULD BE TERMINATED OR "BLINDED" BEFORE RUNNING THIS
DIAGNOSTIC. THE H3190 TURN AROUND CONNECTOR FUNCTIONS AS A TERM-
INATOR.
- DEVICE
This program will be runnable only on a VAX family computer and VAX
Diagnostic Supervisor Version 6.10 or greater. This program will
not support any device other than the DZ11.
- REQUIREMENTS
HARDWARE
VAX PROCESSOR WITH MINIMUM CONFIGURATION
DZ11 M7819 (EIA) OR M7814 (20MA)
OPTIONAL HARDWARE:
H327 TURN AROUND CONNECTOR FOR USE WITH M7819 (EIA)
H3190 TURN AROUND CONNECTOR FOR USE WITH M7814 (20MA)
NOTE: TURN OFF OR DISCONNECT ALL TERMINALS CONNECTED TO THE DZ11 UNDER
TEST, BEFORE RUNNING THE DIAGNOSTIC. CPU CLOCK MUST NOT BE
MARGINED.
IMPORTANT: M7814 (20MA) DZ11 MUST NOT HAVE OPEN RECEIVE LINES.
ALL RECEIVE LINES MUST BE "BLINDED".
SOFTWARE
This program will be runnable only on a VAX family computer
and VAX Diagnostic Supervisor Version 6.10 or greater.
The VAX Diagnostic Supervisor version 6.10 or later
must be resident in memory. This diagnostic may be loaded and
started after the supervisior is running.
This diagnostic is intended to test only the DZ11 product
that is attached to a VAX 11/780, 11/750, or 11/730 processor.
and must include the following:
- ATTACHING
THE FOLLOWING IS AN EXAMPLE OF HOW TO ATTACH THE DEVICE TO
BE TESTED, AND TO LOAD AND RUN EVDAA (ANSWERS TO HARDWARE QUESTIONS
ARE TYPED IN OCTAL) :
DIAGNOSTIC SUPERVISOR. ZZ-ENSAA-6.10-YYY 9-OCT-1983 09:40:14.80
DS> ATT DW730 SBI DW0 5 7 ; ATTACH THE UBA ON THE SBI, VAX/780
OR
DS> ATT DW750 HUB DW0 ; FOR VAX/750 TESTING
OR
DS> ATT DW730 HUB DW0 ; FOR VAX/730 TESTING
DS> LOAD EVDAA ; LOAD THE DIAGNOSTIC
DS> ATT DZ11 ; ATTACH THE DZ11
DEVICE LINK? DW0 ; THE OPTION IS LINKED TO THE UBA
DEVICE NAME? TTA ; THE OPTION IS NAMED UNIT A (RANGE=A-Z)
CSR? 760170 ; THE CSR ADRS IS 760170 (RANGE=760000-777770)
VECTOR? 300 ; VECTOR ADRS IS 300 (RANGE=000-770)
BR? 5 ; BR INTERRUPT LEVEL IS 5 (RANGE=4-7)
MODULE TYPE? EIA ;EIA OR 20MA?
DS> SEL TTA ; SELECT DEVICE
DS> STA
THE PROGRAM SHOULD NOW BE RUNNING.
- SECTIONS
There are two sections to this diagnostic:
o Default Section - Used for all "Normal" testing. (Internal
Loopback). Tests 1 - 19
o Section "ALL" _ Used to test external loopback.
Tests 1 - 21 are run in the Section "ALL".
- TESTS
TEST DESCRIPTIONS
THIS PROGRAM CONSISTS OF 21 TEST IN FIVE SECTIONS. THE DEFAULT
SECTION INCLUDES TEST 1 THRU 19. SECTION "ALL" INCLUDES TEST 1
THRU 21 AND REQUIRES A H327 TURN AROUND CONNECTOR FOR M7819 MODULES
AND A H3190 TURN AROUND CONNECTOR FOR M7814 MODULES. SECTION "MODEM"
IS TEST 20 AND REQUIRES A H327 TURN AROUND CONNECTOR FOR USE WITH
M7819 MODULE. (TEST 20 IS SKIPPED FOR M7814 MODULES.) SECTION "H327"
IS TEST 20 AND 21 AND REQUIRES A H327 TURN AROUND CONNECTOR. SECTION
"H3190" IS TEST 21 AND REQUIRES A H327 TURN AROUND CONNECTOR FOR
M7819 MODULES AND A H3190 TURN AROUND CONNECTOR FOR M7814 MODULES.
6.1 TEST 1 SUBTEST 1 CSR REGISTER TEST PART ONE
TEST DESCRIPTION:
THIS SUBTEST CHECKS THE ABILITY OF THE DIAGNOSTIC TO READ AND
WRITE THE DEVICE CSR REGISTER.
TEST STEPS:
1. FORCE UNIBUS RESET
2. READ ALL CSR BITS VERIFY ALL ZEROS
3. MOVW ONES TO ALL CSR R/W BITS AND VERIFY ALL ONES
(EXCLUDE CLEAR BIT)
6.2 TEST 1 SUBTEST 2 CSR REGISTER TEST PART TWO
TEST DESCRIPTION:
THIS TEST, USING SEVERAL PATTERNS, AND SEVERAL INSTRUCTIONS TEST
EACH READ WRITE BIT IN THE CSR.
TEST STEPS:
1. USING DATA FROM TEST TABLE CSR_TST1_DTA$W MOVW TO CSR
AND VERIFY
2. MOVW 5068 TO CSR AND VERIFY
3. ASSERT UNIBUS RESET VERIFY CSR ALL ZEROS
4. USING DATA FROM TEST TABLE CSR_TST2_DTA$W BISW IN CSR
AND VERIFY
5. USING DATA FROM TEST TABLE CSR_TST2_DTA$2 BICW IN CSR
AND VERIFY
6. MOVW 5068 TO CSR AND VERIFY
7. BISW 04 AND VERIFY ALL BITS ARE ZERO
8. MOVB 68 TO CSR AND VERIFY
9. MOVB 50 TO CSR AND VERIFY (US ODD BYTE ADDRESS)
6.3 TEST 2 TCR REGISTER TEST
TEST DESCRIPTION:
THIS TEST, USING SEVERAL PATTERNS, MOVW'S TO/FROM ,BIS, AND BIC
TO TCR. THE TEST RECOGNIZES THE DIFFERENCES BETWEEN THE M7819
AND M7814 MODULES. (M7819 HAS A 16 BIT TCR WHILE THE M7814 HAS
A 8 BIT TCR.)
TEST STEPS:
1. MOVB ONES TO TCR AND VERIFY ALL ONES
2. MOVB ZEROS TO TCR AND VERIFY ALL ZEROS
3. MOVB ONES TO TCR AND ASSERT UNIBUS INIT
VERIFY ALL BITS ARE ZERO
4. MOVB ONES TO TCR AND ASSERT DZ CLEAR
VERIFY ALL BITS ARE ZERO
5A. BISB FIRST BIT TO RIGHT
5B. MOVB FROM TCR AND VERIFY ONLY SELECTED BIT SET
6. SHIFT BIT LEFT ONE REPEAT STEP 5
7A. BICB TCR BIT
7B. MOVB FROM TCR AND VERIFY SELECTED BIT CLEARED
8. SHIFT BIT LEFT ONE AND REPEAT STEP 7
6.4 TEST 3 TRANSMIT READY FLAG TEST PART ONE
TEST DESCRIPTION:
THIS TEST VERIFIES THE CORRECT FUNCTIONING OF TRANSMIT READY.
THE TEST CHECKS ONLY LINE ZERO.
TEST STEPS:
1. MOVW ZEROS TO LPR (RX OFF, 50 BAUD, NO PARITY,
ONE STOP BIT, T BIT WORD, LINE 0)
2. MOVB 01 TO TCR EVEN BYTE (ENABLE LINE 0)
3. MOVW 0020 TO CSR (MAST SCAN ENAB)
4. IF 'TX RDY' BEFORE TIMEOUT THEN NEXT STEP ELSE
PRINT 'TX RDY' FAILED TO SET
5. MOVW ZEROS TO TDR
6. TST CSR IF NEGATIVE THEN PRINT 'TX RDY' FAILED TO RESET
ELSE GOTO NEXT STEP
7. TST CSR IF POSITIVE THEN PRINT 'TX RDY' FAILED TO SET
ELSE GOTO NEXT STEP (TX RDY SHOULD SET AGAIN AFTER
CHARACTER HAS BEEN TRANSMITTED)
8. MOVB ZEROS TO TCR EVEN BYTE (DISABLE LINE 0)
9. TST CSR IF NEGATIVE THEN PRINT 'TX RDY' FAILED TO RESET
ELSE GOTO NEXT SUBTEST
6.5 TEST 4 TRANSMIT INTERRUPT TEST PART ONE
TEST DESCRIPTION:
THIS TEST VERIFIES THAT THE DEVICE WILL INTERRUPT WHEN A
CHARACTER IS REQUIRED FOR TRANSMISSION. THE INTERRUPT HANDLER
CHECKS THE VECTOR ADDRESS AGAINST THAT CONTAINED IN THE HARDWARE
PARAMETER TABLE AND WILL PRINT AN ERROR MESSAGE IF A MISS MATCH
OCCURS. ALSO, THE INTERRUPT HANDLER CHECKS THE "BR" LEVEL
AGAINST THE HARDWARE PARAMETER TABLE AND PRINTS ANY MISS MATCHES.
TEST STEPS:
1. MOVW ZEROS TO LPR (RX OFF, 50 BAUD, NO PARITY,
ONE STOP BIT, 5 BIT WORD, LINE 0)
2. MOVB 01 TO TCR EVEN BYTE (ENABLE LINE 0)
3. MOVW 4020 TO CSR (TX INTR ENAB, MAST SCAN ENAB)
4. IF INTERRUPT BEFORE TIMEOUT THEN NEXT STEP ELSE
PRINT TRANSMIT INTERRUPT FAILURE
5. THEN PRINT TRANSMIT VECTOR
6. MOVW ZEROS TO TDR
7. IF INTERRUPT BEFORE TIMEOUT THEN NEXT STEP ELSE
PRINT TRANSMIT INTERRUPT FAILURE
8. COMPARE PREVIOUS VECTOR TO CURRENT VECTOR PRINT
ERROR IF NOT THE SAME
6.6 TEST 5 MAINTENANCE MODE TEST PART ONE
TEST DESCRIPTION:
THIS TEST VERIFIES THAT A CHARACTER CAN BE TRANSMITTED AND
RECEIVED ERROR FREE USING THE MAINTENANCE MODE. RECEIVE DONE
FLAG IS CHECK IN THIS TEST.
TEST STEPS:
1. MOVW 1000 TO LPR (RX ON, 50 BAUD, NO PARITY,
ONE STOP BIT, 5 BIT WORD, LINE ZERO)
2. MOVB 01 TO TCR (ENABLE LINE ZERO)
3. MOVW 4028 TO CSR (TX INTR ENAB, MAST SCAN ENAB,
MAINT)
4. AFTER TRANSMIT INTERRUPT MOVW ZEROS TO TDR
5. TSTB CSR EVEN BYTE (RX DONE)
6. IF 'RX DONE' BEFORE TIMEOUT THEN GOTO STEP 7 ELSE 9
7. MOVW FROM RBUF IF 'DATA VALID' THEN STEP 8
ELSE STEP 11
8. COMPARE RECEIVE DATA TO TRANSMIT DATA PRINT ERROR
IF DIFFERENT ELSE EXIT
9. IF STEP 6 TIMEOUT THEN MOVW FROM RBUF
10. IF 'DATA VALID' THEN 'RX DONE' FAILED TO SET
ELSE NEXT STEP
11. MAINT MODE FAILURE
6.7 TEST 6 RECEIVE INTERRUPT TEST PART ONE
TEST DESCRIPTION:
THIS TEST VERIFIES THAT THE DEVICE WILL INTERRUPT WHEN A
CHARACTER IS AT THE BOTTOM OF THE SILO. THE INTERRUPT HANDLER
CHECKS THE VECTOR ADDRESS AGAINST THAT CONTAINED IN THE HARDWARE
PARAMETER TABLE AND WILL PRINT AN ERROR MESSAGE IF A MISS MATCH
OCCURS. ALSO, THE INTERRUPT HANDLER CHECKS THE "BR" LEVEL
AGAINST THE HARDWARE PARAMETER TABLE AND PRINTS ANY MISS MATCHES.
TEST STEPS:
1. MOVW ZEROS TO LPR (RX OFF, 50 BAUD, NO PARITY,
ONE STOP BIT, 5 BIT WORD, LINE ZERO)
MAINT MODE)
2. MOVB 01 TO TCR (ENABLE LINE 0)
3. MOVW 0068 TO CSR (RX INTR ENAB, MAST SCAN ENAB,
4. MOVW ZEROS TO TDR
5. IF RECEIVE INTERRUPT BEFORE TIMEOUT THEN PRINT VECTOR
6. MOVW 4068 TO CSR (TX INTR ENAB, RX INTR ENAB,
MAST SCAN ENAB, MAINT MODE)
7. IF TRANSMIT INTERRUPT BEFORE TIMEOUT THEN MOVW ZEROS
TO TDR ELSE PRINT TRANSMIT INTERRUPT FAILURE
8. IF TRANSMIT INTERRUPT BEFORE RECEIVE INTERRUPT REPORT
ERROR ELSE NEXT SUBTEST
9. XOR TRANSMIT VECTOR WITH RECEIVE VECTOR
10. TEXT VECTOR ADDRESS BIT 2 OF RESULTANT OF STEP 9
IF SET NEXT STEP ELSE PRINT VECTOR ADDRESS ERROR
11. CLEAR VECTOR ADDRESS BIT 2 OF RESULTANT
12. SUBTEST RESULANT OF STEP 11 IF ZERO NEXT SUBTEST ELSE
PRINT VECTOR ADDRESS ERROR
6.8 TEST 7 RECEIVE INTERRUPT TEST PART TWO
TEST DESCRIPTION:
THIS TEST VERIFIES THAT A RECEIVE INTERRUPT WILL TAKE
PRECEDENCE OVER A TRANSMIT INTERRUPT IN CASE OF TIES.
TEST STEPS:
1. CLEAR ANY PENDING UBA STATUS
2. ENABLE UBA INTERRUPTS
3. LOAD LINE 0 LPR
4. SETUP TRANSMIT AND RECEIVE BUFFERS
5. ENABLE DEVICE WITH DEVICE INTERRUPTS OFF
6. LOAD TDR
7. WAIT FOR RECEIVE DONE FLAG TO SET
8. ENABLE DEVICE TRANMIT AND RECEIVE INTERRUPTS
9. VERIFY THAT RECEIVE INTERRUPT OCCURRED FIRST
6.9 TEST 8 TRANSMIT READY FLAG TEST PART TWO
TEST DESCRIPTION:
THIS TEST IS A REPEAT OF TEST 3 BUT CHECKS ALL EIGHT LINES. THE
TEST VERIFIES THE CORRECT LINE NUMBER IN THE CSR FOR EACH LINE.
TEST STEPS:
1. MOVW ZEROS TO LPR (RX OFF, 50 BAUD, NO PARITY,
ONE STOP BIT, T BIT WORD, LINE 0)
2. MOVB 01 TO TCR EVEN BYTE (ENABLE LINE 0)
3. MOVW 0020 TO CSR (MAST SCAN ENAB)
4. IF 'TX RDY' BEFORE TIMEOUT THEN NEXT STEP ELSE
PRINT 'TX RDY' FAILED TO SET
5. MOVB ZEROS TO TDR
6. TST CSR IF NEGATIVE THEN PRINT 'TX RDY' FAILED TO RESET
ELSE GOTO NEXT STEP
7. TST CSR IF POSITIVE THEN PRINT 'TX RDY' FAILED TO SET
ELSE GOTO NEXT STEP (TX RDY SHOULD SET AGAIN AFTER
CHARACTER HAS BEEN TRANSMITTED)
8. MOVB ZEROS TO TCR EVEN BYTE (DISABLE LINE 0)
9. TST CSR IF NEGATIVE THEN PRINT 'TX RDY' FAILED TO RESET
ELSE GOTO NEXT SUBTEST
6.10 TEST 9 TRANSMIT INTERRUPT TEST PART TWO
TEST DESCRIPTION:
THIS IS A REPEAT OF TEST 4 BUT CHECKS ALL EIGHT LINES
TEST STEPS:
1. MOVW ZEROS TO LPR (RX OFF, 50 BAUD, NO PARITY,
ONE STOP BIT, 5 BIT WORD, LINE 0)
2. MOVB 01 TO TCR EVEN BYTE (ENABLE LINE 0)
3. MOVW 4020 TO CSR (TX INTR ENAB, MAST SCAN ENAB)
4. IF INTERRUPT BEFORE TIMEOUT THEN NEXT STEP ELSE
PRINT TRANSMIT INTERRUPT FAILURE
5. THEN PRINT TRANSMIT VECTOR
6. MOVW ZEROS TO TDR
7. IF INTERRUPT BEFORE TIMEOUT THEN NEXT STEP ELSE
PRINT TRANSMIT INTERRUPT FAILURE
8. COMPARE PREVIOUS VECTOR TO CURRENT VECTOR PRINT
ERROR IF NOT THE SAME
6.11 TEST 10 BAUD RATE TIMING TEST
TEST DESCRIPTION:
THIS TEST RUNS MESSAGES AT ALL THE SPEEDS FROM 50 TO 9600, AND
THOUGH ALL CHARACTER SIZES FROM 5 TO 8. THE MESSAGES ARE SENT IN
THE FOLLOWING ORDER : 50 BITS PER SEC & 8-BIT CHARS, 50 BPS & 7
BITS, 50 BPS & 6 BITS, 50 BPS & 5 BITS, 75 BPS & 5 BITS, 110 BPS
& 5 BITS, 134.5 BPS & 5 BITS, 150 BPS & 5 BITS, 300 BPS & 5 BITS,
600 BPS & 5 BITS, 1200 BPS & 5 BITS, 1800 BPS & 5 BITS, 2000 BPS
& 5 BITS, 2400 BPS & 5 BITS, 3600 BPS & 5 BITS, 4800 BPS & 5 BITS,
7200 BPS & 5 BITS, 9600 BPS & 5 BITS.
EACH MESSAGE IS COMPARED TO PREVIOUS MESSAGE TO NOTE THE RELATIVE
DIFFERENCE IN TIME, SINCE THERE IS NO WAY TO ACCURATELY TIME THE
ACTUAL SPEED OF THE TRANSMISSIONS DUE TO DIFFERENCES IN PROCESSOR
TYPES, ETC. THIS TEST WILL GUARANTEE THAT 9600 BAUD IS FASTER THAN
4800, ETC., AND THAT 5 BITS PER CHAR IS FASTER THAN 8 BITS PER
CHAR, ETC.
IF PROGRAMMABLE LOCAL MODEM LOOPBACK OR "OTHER PER-LINE EXTERNAL
LOOPBACK" IS SELECTED, THIS TEST IS SKIPPED.
** NOTE : ** THIS TEST CAN TAKE UP TO 4.5 MINUTES TO RUN, ON A
SLOW PROCESSOR.
TEST STEPS:
6.12 TEST 11 MAINTENANCE MODE SUBTEST PART TWO
TEST DESCRIPTION:
THIS IS A REPEAT OF TEST 5 BUT FOR ALL EIGHT LINES. THE CORRECT
LINE NUMBER IS VERIFIED IN THE RBUF FOR EACH LINE.
TEST STEPS:
1. MOVW 1E00 TO LPR (RX ON, 9.6K BAUD, NO PARITY,
ONE STOP BIT, 5 BIT WORD, LINE ZERO)
MAINT MODE)
2. MOVB 01 TO TCR (ENABLE LINE 0)
3. MOVW 0068 TO CSR (RX INTR ENAB, MAST SCAN ENAB,
4. MOVW ZEROS TO TDR
5. IF 'RX INTR' BEFORE TIMEOUT THEN GOTO STEP 6 ELSE 9
6. MOVW FROM RBUF IF 'DATA VALID' THEN STEP 7
ELSE STEP 11
7. COMPARE RECEIVE DATA TO TRANSMIT DATA PRINT ERROR
IF DIFFERENT
8. INCREMENT LINE NUMBER AND REPEAT 4 THRU 7 FOR
ALL LINES
9. IF STEP 5 TIMEOUT THEN MOVW FROM RBUF
10. IF 'DATA VALID' THEN 'RX DONE' FAILED TO SET
ELSE NEXT
11. MAINT MODE FAILURE
6.13 TEST 12 RECEIVE INTERRUPT TEST PART THREE
TEST DESCRIPTION:
THIS TEST IS A REPEAT OF TEST 6 BUT FOR ALL EIGHT LINES.
TEST STEPS:
1. MOVW 1000 TO LPR (RX ON, 50 BAUD, NO PARITY,
ONE STOP BIT, 5 BIT WORD, LINE 0)
2. MOVB 01 TO TCR (ENABLE LINE 0)
3. MOVW 0068 TO CSR (RX INTR ENAB, MAST SCAN ENAB,
MAINT MODE)
4. MOVW ZEROS TO TDR
5. IF RECEIVE INTERRUPT BEFORE TIMEOUT THEN NEXT, ELSE ERROR
6. BISB2 BIT 14 TO CSR (TX INTR ENAB, RX INTR ENAB,
MAST SCAN ENAB, MAINT MODE)
MAKE SEPARATE SUBTEST 'RECEIVE INTERRUPT SUBTET PART THREE
7. MOVW ZEROS TO TDR
8. IF TRANSMIT INTERRUPT BEFORE RECEIVE INTERRUPT REPORT
ERROR ELSE NEXT
9. INCREMENT LINE NUMBER REPEAT 3 THRU 8 FOR ALL LINES
6.14 TEST 13 CHARACTER LENGTH TEST
TEST DESCRIPTION:
THIS TEST VERIFIES THAT ALL LINES CAN TRANSMIT CHARACTERS OF
LENGTH 5, 6, 7, AND 8 BITS.
TEST STEPS:
1. MOVW 1E00 TO LPR (RX ON, 9.6K BAUD, NO PARITY,
ONE STOP BIT, 5 BIT WORD, LINE 0.)
2. ENABLE LINE ZERO
3. SET TRANSMIT BUFFER FOR A CHARACTER OF FF HEX
4. TRANSMIT FOUR CHARACTERS
5. CHECK RECEIVE DATA FOR CORRECT DATA
6. INCREMENT WORD LENGTH AND REPEAT STEPS 1 THRU 5
7. AFTER WORD LENGTH 8 INCREMENT LINE NUMBER AND REPEAT
STEPS 1 THRU 6 FOR REMAINING LINES
6.15 TEST 14 STOP BIT TEST
TEST DESCRIPTION:
THIS TEST VERIFIES THAT ALL LINES CAN BE SET FOR 1 AND 2
(1 1/2 FOR 5 BIT WORD LENGTH) STOP BITS. THE TEST CAN NOT
VERIFY THAT THE UARTS ACTUAL TRANSMIT THE CORRECT NUMBER OF
STOP BITS.
TEST STEPS:
1. MOVW 1E00 TO LPR (RX ON, 9.6K BAUD, NO PARITY,
ONE STOP BIT, 5 BIT WORD, LINE 0)
2. MOVB 01 TO TCR (ENABLE LINE 0)
3. MOVW 0068 TO CSR (RX INTR ENAB, MAST SCAN ENAB,
MAINT MODE)
4. MOVW ZEROS TO TDR
5. MOVW FROM RBUF CHECK FOR 'DATA VALID' AND 'NOT FRAM
ERR'
6. IF NO ERROR THEN NEXT STEP ELSE PRINT ERROR
7. MOVW 1E20 TO LPR (RX ON, 9.6K BAUD, NO PARITY,
1 1/2 STOP BITS, 5 BIT WORD)
8. CHECK FOR FRAMING ERROR
9. REPEAT 3 THRU 7 FOR ALL LINES
10. MOVW 1E38 TO LPR (RX ON, 9.6K BAUD, NO PARITY,
TWO STOP BITS, 8 BIT WORD LENTGH, LINE 0)
11. CHECK FOR FRAMING ERROR REPEAT FOR ALL LINES
6.16 TEST 15 PARITY BIT TEST
TEST DESCRIPTION:
THE TEST VERIFIES THAT THE UARTS CAN BE SET TO EVEN, ODD, AND
NO PARITY.
(THE H327 OR H3190 TEST VERIFY THAT THE UARTS CAN DETECT PARITY
ERRORS.)
TEST STEPS:
1. MOVW 1E58 TO LPR (RX ON, 9.6K BAUD, EVEN
PARITY, ONE STOP BIT, 8 BIT WORD, LINE 0)
2. USING SEVERAL PATTERNS TRANSMIT CHARACTERS AND CHECK FOR
PARITY ERRORS
3. REPEAT FOR ALL LINES
4. MOVW 1ED8 TO LPR (RX ON, 9.6K BAUD, ODD PARITY,
ONE STOP BIT, 8 BIT WORD, LINE 0)
5. USING SEVERAL PATTERNS TRANSMIT CHARACTERS AND CHECK FOR
PARITY ERROR
6. REPEAT FOR ALL LINES
6.17 TEST 16 OVERRUN BIT TEST
TEST DESCRIPTION:
THIS TEST VERIFIES THAT THE UARTS CAN DETECT AN OVER RUN
CONDITION. THIS IS ACCOMPLISHED BY TRANSMITTING A BLOCK
OF 66 CHARACTERS WITH RECEIVE INTERRUPTS DISABLED.
TEST STEPS:
1. MOVW 1ED8 TO LPR (RX ON, 9.6K BAUD, ODD PARITY,
ONE STOP BIT, 8 BIT WORD, LINE 0)
2. MOVW 4028 TO CSR (TX INTR ENAB, MAST SCAN ENAB, MAINT
MODE)
3. MOVB TO TCR (ENABLE SELECTED LINE)
4. RUN A BLOCK OF CHARACTERS TO SEECTED LINE WHILE
IN MAINT MODE
5. COMPARE TRANSMIT BUFFER TO RECEIVE BUFFER IF DIFFERENT
PRINT DATA COMPARE ERROR ELSE NEXT STEP
6. INCREMENT LINE NUMBER
7. REPEAT SUBTEST USING INCREMENTED LINE
6.18 TEST 17 LPR BYTE ACCESS TEST
TEST DESCRIPTION:
THIS TEST VERIFIES THAT THE LPR'S WILL NOT CHANGE IF REFERENCED
BY A BYTE INSTRUCTION.
TEST STEPS:
1. MOVW 1E00 TO LPR
2. MOVB ODD 00 TO LPR
3. TRANSMIT AND RECEIVE TWO CHARACTERS
4. IF RECEIVE INTERRUPTS STOP THEN ERROR
ELSE NEXT STEP
5. MOVB EVEN 30 TO LPR
6. TRANSMIT AND RECEIVE TWO CHARACTERS
7. IF CHARACTER GREATER THAN 5 BITS LONG THEN
ERROR ELSE EXIT
6.19 TEST 18 SUBTEST 1 SILO BIT TEST
TEST DESCRIPTION:
THIS TEST CHECKS FOR STUCK AT ONE OR ZERO BITS IN THE 64
LOCATIONS OF THE SILO. THE TEST USES FOUR LINES TO CHECK
THE SILO.
TEST STEPS:
1. MOVW 1EDA TO LPR (RX ON, 9.6K BAUD, ODD PARITY
ONE STOP BIT, 8 BIT WORD, LINE 2)
2. MOVW 1EDD TO LPR (RX ON, 9.6K BAUD, ODD PARITY
ONE STOP BIT, 8 BIT WORD, LINE 5)
3. MOVB 24 TO TCR (ENABLE LINE 2 AND LINE 5)
4. MOVW 4028 TO CSR (TX INTR ENAB, MAST SCAN ENAB,
MAINT MODE)
5. TRANSMIT 64 CHARACTERS IN A PATTERN TO CHECK SILO
(LINE 2 TRANSMITS 32 BYTES OF AA HEX AND LINE 5 TRANSMITS
32 BYTES OF 55 HEX)
6. MOVW 1ED8 TO LPR (RX ON, 9.6K BAUD, ODD PARITY
ONE STOP BIT, 8 BIT WORD, LINE 0)
7. MOVW 1EDF TO LPR (RX ON, 9.6K BAUD, ODD PARITY
ONE STOP BIT, 8 BIT WORD, LINE 7)
8. TRANSMIT 64 CHARACTERS IN A PATTERN TO CHECK SILO
(LINE 0 TRANSMITS 32 BYTES OF ZEROS AND LINE 7 TRANSMITS
32 BYTES OF FF HEX)
NOTE: SILO BITS 13 AND 12 ARE NOT CHECKED BY THIS TEST
USE H327 OR H3190 TEST TO CHECK BITS 13 AND 12
6.20 TEST 18 SUBTEST 2 SILO ALARM TEST
TEST DESCRIPTION:
THIS TEST VERIFIES THAT SILO ALARM WILL NOT SET UNTIL THE
SIXTEENTH CHARACTER HAS BEEN RECEIVED.
TEST STEPS:
1. MOVW 1ED8 TO LPR (RX ON, 9.6K BAUD, ODD PARITY
ONE STOP BIT, 8 BIT WORD, LINE 0)
2. MOVW 5068 TO CSR (TX INTR ENAB, SILO ALARM,
RX INTR ENAB, MAST SCAN ENAB, MAINT MODE)
3. MOVB 01 TO TCR (ENABLE LINE 0)
4. TRANSMIT 15 CHARACTERS SHOULD BE NO SILO INTERRUPT
5. CLEAR DZ11 DO STEPS 1, 2, AND 3
6. TRANSMIT 16 CHARACTERS SHOULD GET SILO INTERRUPT
6.21 TEST 18 SUBTEST 3 UART TRANSFER TEST
TEST DESCRIPTION:
THIS TEST, STARTING WITH LINE 0 AND SEQUENTIALLY TESTING EACH
LINE THRU LINE 7, IS A DATA RELIABLILITY TEST FOR ALL EIGHT
UARTS.
TEST STEPS
1. MOVW 1ED8 TO LPR (RX ON, 9.6K BAUD, ODD PARITY,
ONE STOP BIT, 8 BIT WORD, LINE 0)
2. MOVW 1068 TO CSR (TX INTR ENAB, RX INTR ENAB,
MAST SCAN ENAB, MAINT MODE)
3. MOVB TO TCR (ENABLE SELECTED LINE)
4. RUN A BLOCK OF CHARACTERS TO SEECTED LINE WHILE
IN MAINT MODE
5. COMPARE TRANSMIT BUFFER TO RECEIVE BUFFER IF DIFFERENT
PRINT DATA COMPARE ERROR ELSE NEXT STEP
6. INCREMENT LINE NUMBER
7. REPEAT SUBTEST USING INCREMENTED LINE
6.22 TEST 19 SUBTEST 1 FAST BAUD RATE TEST
INTERMITTENT ERRORS WILL OCURR ON M7814 (20MA) DZ11'S,
IF ANY RECEIVE LINES ARE LEFT UNTERMINATED. THE RECEIVE
INPUTS CAN BE CONNECTED TO TERMINALS, "BLINDED", OR THE
H3190 TURN CONNECTOR INSTALLED. IT IS CONSIDERED GOOD
PRACTICE TO NEVER LEAVE 20MA LINES UNTERMINATED.
TEST DESCRIPTION:
THIS IS THE FIRST TEST THAT RUNS ALL EIGHT LINES CONCURRENTLY.
AN ATTEMPT IS MADE TO FIND ANY INTERACTION ERRORS IN THIS AND
THE FOLLOWING TEST IN THIS SECTION.
TEST STEPS:
1. SET UP EIGHT DIFFERENT PATTERNS IN 8 TRANSMIT
BUFFERS
2. SET ALL LINES FOR 9.6K BAUD, 8 BIT WORD,
ONE STOP BIT, ODD PARITY,
3. ENABLE ALL LINES TRANSMIT A BLOCK OF DATA
4. COMPARE ALL TRANSMIT BUFFERS TO ALL RECEIVE BUFFERS
5. IF ANY MISCOMPARES PRINT DATA ERROR AND LINE NUMBER
ELSE NEXT SUBTEST
6.23 TEST 19 SUBTEST 2 DYNAMIC BAUD RATE CHANGE TEST
TEST DESCRIPTION:
THIS TEST SETS 7 LINES FOR 9.6K BAUD AND 1 FOR 50 BAUD. THEN A
BLOCK OF CHARACTERS IS TRANSMITTED ON ALL LINES. THE NUMBER OF
CHARCTERS RECEIVED IS CHECKED TO VEIRFY THAT ALL LINES WHERE
FUNCTIONING AT THE CORRECT BAUD RATE. THE DATA IS CHECKED FOR
ERRORS. THIS TEST IS REPEATED UNTIL ALL LINES HAVE BEEN CHECKED
AT 50 BAUD.
TEST STEPS:
1. SET UP 7 LINES FOR 9.6K BAUD, 8 BIT WORD, ONE
STOP BIT, ODD PARITY.
2. SET LINE UNDER SUBTEST TO 50 BAUD, 8 BIT WORD, ONE
STOP BIT, ODD PARITY
3. ENABLE ALL LINES AND BEGAN TRANSFER A BLOCK OF DATA
4. IF NO ERROR RESTORE LINE UNDER SUBTEST TO 9.6K BAUD
5. INCREMENT LINE NUMBER
6. REPEAT SUBTEST FOR ALL LINES
6.24 TEST 19 SUBTEST 3 DYNAMIC WORD LENGTH TEST
TEST DESCRIPTION:
THIS TEST SETS 7 LINES TO 8 BIT WORD LENGTH AND ONE FOR 5 BIT.
THEN A BLOCK OF CHARACTERS IS TRANMITTED. THE DATA IS CHECKED
FOR ERRORS. THE TEST IS REPEATED UNTIL ALL LINES HAVE BEEN
CHECKED AT 5 BIT WORD LENGTH.
TEST STEPS:
1. SET UP 7 LINES FOR 9.6K BAUD, 8 BIT WORD, ONE
STOP BIT, ODD PARITY
2. SET LINE UNDER SUBTEST TO 5 BIT WORD LENGTH
3. ENABLE ALL LINES AND TRANSFER A BLOCK OF DATA
(3 MSB BITS OF DATA SHOULD BE ALL ONES)
4. IF NO ERRORS RESTORE LINE UNDER SUBTEST TO 8 BIT WORD
(3 MSB BITS SHOULD BE ZEROS FOR SELECTED LINE)
5. INCREMENAT LINE NUMBER
6. REPEAT SUBTEST FOR ALL LINES
6.25 TEST 19 SUBTEST 4 DYNAMIC STOP BIT TEST
TEST DESCRIPTION:
THIS TEST IS A VARIATION OF SUBTEST 3 BUT THE LINES ARE CHECKED
BY USING DIFFERENT STOP BITS.
TEST STEPS:
1. SET UP 7 LINES FOR 9.6K BAUD, 8 BIT WORD, ONE
STOP BIT, ODD PARITY
2. SET LINE UNDER SUBTEST TO 2 STOP BITS
3. ENABLE ALL LINES AND TRANSFER A BLOCK OF DATA
4. IF NO ERRORS RESTORE LINE UNDER SUBTEST TO 1 STOP BIT
5. INCREMENT LINE NUMBER
6. REPEAT FOR ALL LINES
6.26 TEST 19 SUBTEST 5 DYNAMIC PARITY TEST
TEST DESCRIPTION:
THIS TEST IS A VARIATION OF SUBTEST 3 WITH PARITY
TEST STEPS:
1. SET UP 7 LINES FOR 9.6K BAUD, 8 BIT WORD, ONE
STOP BIT, ODD PARITY
2. SET LINE UNDER SUBTEST TO EVEN PARITY
3. ENABLE ALL LINES AND TRANSFER A BLOCK OF DATA
4. IF NO ERROR RESTORE LINE UNDER SUBTEST TO ODD PARITY
5. REPEAT FOR ALL LINES
6.27 TEST 20 MODEM CONTROL TEST
(REQUIRES MANUAL INTERVENTION AND H327 TURN AROUND
CONNECTOR. TEST IS FOR M7819(EIA) MODULES ONLY)
TEST DESCRIPTION:
THIS TEST CHECKS THE MODEM CONTROL SIGNALS DATA TERMINAL READY,
RING INDIACTOR, AND CARRIER DETECTED. A H327 TURN AROUND TEST
CONNECTOR MUST BE INSTALLED BEFORE RUNNING THIS TEST.
TEST STEPS:
1. ASSERT DTR0 SHOULD SEE RI1 AND CO1
2. ASSERT DTR1 SHOULD SEE RI0 AND CO0
3. REPEAT FOR ALL LINE PAIRS
6.28 TEST 21 SUBTEST 1 H327/H3190 FAST BAUD RATE TEST
NOTE:
(THE H327 TURN AROUND CONNECTOR SHOULD BE INSTALLED ON THE
END OF THE FLAT RIBBON CABLE ATTACHED TO THE M7819 MODULE.)
(THE H3190 TURN AROUND CONNECTOR SHOULD BE INSTALLED ON THE
END OF THE FLAT RIBBON CABLE ATTACHED TO THE M7814 MODULE.)
TEST DESCRIPTION:
THIS TEST VERIFIES THAT THE DEVICE CAN TRANSFER A BLOCK OF
CHARACTERS ERROR FREE USING THE H327 OR H3190 TURN AROUND
CONNECTOR.
TEST STEPS:
1. SET UP EIGHT DATA PATTERNS IN EIGHT TRANSMIT
BUFFERS
2. SET ALL LINES FOR 9.6K BAUD, 8 BIT WORD,
ONE STOP BIT, NO PARITY ON FIRST PASS,
EVEN PARITY ON SECOND PASS, AND ODD PARITY ON LAST PASS
3. ENABLE ALL LINES TRANSMIT A BLOCK OF DATA
4. COMPARE ALL TRANSMIT BUFFERS TO ALL RECEIVE BUFFERS
5. IF ANY MISCOMPARES PRINT DATA ERROR AND LINE NUMBER
ELSE NEXT SUBTEST
6. REPEAT SUBTEST WITH EVEN PARITY
7. REPEAT SUBTEST WITH ODD PARITY
6.29 TEST 21 SUBTEST 2 H327/H3190 PARITY ERROR TEST
TEST DESCRIPTION:
THIS TEST CHECKS THE UARTS ABILITY TO DETECT PARITY ERRORS
TEST STEPS:
1. SET LINE 0 FOR EVEN PARITY AND LINE 1 FOR ODD PARITY
2. TRANSMIT CHARACTER SHOULD SEE PARITY ERROR
3. REPEAT FOR ALL LINE PAIRS
4. SET LINE 0 FOR ODD PARITY AND LINE 1 FOR EVEN PARITY
5. TRANSMIT CHARACTER SHOULD SEE PARITY ERROR
6. REPEAT FOR ALL LINES PAIRS
6.30 TEST 21 SUBTEST 3 H327/H3190 BREAK BIT TEST
TEST DESCRIPTION:
- THIS TEST VERIFIES THAT SETTING A BREAK BIT FOR ANY LINE WILL
BLOCK TRANSMISSIONS FOR THAT LINE.
ASSUMPTIONS:
- DATA PATH TO DEVICE IS IN WORKING ORDER (I.E. CPU, SBI, AND
UBA RUN PROPERLY).
- ALL PREVIOUS TESTS HAVE RUN ERROR FREE.
- ONE OF THE FOLLOWING STAGGERED TURNAROUND CONNECTORS MUST BE
USED FOR THIS TEST:
H3271,H327,H3190, OR H325 STAGGERED TURNAROUND CONNECTOR.
ABSTRACT:
The "BREAK" register is used to apply a continuous zero signal
to the line. The "BREAK BIT", when set, brings the transmitted
data line to the "SPACE" (0) state for as long as the bit is
set. This permits the sending of a special signal, called the
"BREAK" signal. This signal is used by some terminals as a
special control character.
The "BREAK BIT TEST" was designed with the following ideas in
mind:
- Setting the BREAK BIT will not allow the transmission of
characters as long as the bit is set. Any characters loaded
into the transmitter buffer after the BREAK BIT is set, will
not be transmitted. The receiver will expect to see data
followed by a STOP BIT. Instead, all 0's are sent and a
framing error occurs because no STOP BIT was detected.
- All 1's will be loaded into the transmitter buffer after the
BREAK BIT is set. The 1's should never be sent if the BREAK
BIT is operating correctly.
- The "EXPECTED DATA RECEIVED" will include an all 0's
character, and detection of a framing error. This condition
will verify the setting of the BREAK BIT.
- Odd parity will be forced on the transmitted data. If the
BREAK BIT is set properly, the receiver should also indicate
a parity error. Detection of parity error is also included
in the "EXPECTED DATA RECEIVED".
TEST STEPS:
1. Set all line parameters the same.
2. Set BREAK BIT for that line.
3. Transmit all 1's on one line.
4. Set up "EXPECTED DATA RECEIVED" to compare with "ACTUAL
DATA RECEIVED".
5. "ACTUAL DATA" is compared with "EXPECTED DATA". If the data
is not the same, then an error is flagged.
6. Repeat for all lines.
ERRORS:
1. If the "ACTUAL DATA" is not the same as the "EXPECTED DATA",
then an error is flagged.
2. If the RECEIVER DONE BIT fails to set, then an error is
flagged.
6.31 TEST 21 SUBTEST 4 H327/H3190 FRAMING ERROR TEST
TEST DESCRIPTION:
THIS TEST VERIFIES THAT THE UARTS CAN DETECT FRAMING ERRORS.
TEST STEPS:
1. SET LINE 0 FOR ONE STOP BITS LINE 1 FOR TWO STOP
BIT
2. TRANSMIT TWO CHARACTERS WITH NO BREAK BETWEEN CHARACTERS
FROM LINE 0 TO LINE 1
3. LOOK FOR FRAMING ERROR
4. SET LINE 0 FOR TWO STOP LINE 1 FOR ONE STOP BIT
5. TRANSMIT TWO CHARACTERS FROM LINE 1 TO LINE 0 WITH
NO BREAK BETWEEN CHARACTERS.
6. REPEAT FOR ALL LINE PAIRS.
- ERROR_TYPES
- SYSTEM_FATAL_ERRORS
ANY FAILURE ATTEMPTING TO USE SYSTEM SERVICES ARE CONSIDERED
AS SYSTEM FATAL AND BEYOND THE SCOPE OF THIS DIAGNOSTIC.
THE APPROPRIPATE DIAGNOSTIC SHOULD BE RUN TO LOCATE THE PROBLEM.
FOR EXAMPLE IF CHANNEL SERVICES FAIL, THE DW780 DIAGNOSTIC SHOULD
BE RUN.
- DEVICE_FATAL_ERRORS
ALL DEVICE FATAL ERRORS CAN BE PUT INTO A SCOPE LOOP BY SETTING
THE LOOP FLAG.
- HARD_ERRORS
ALL HARD ERRORS CAN BE PUT INTO A SCOPE LOOP BY SETTING THE
LOOP FLAG.
- HISTORY
MODIFIED BY GARY HUFF DATE 15-JUN-1979
VERSION 2.0 MODIFIED TO BE COMPATIBLE WITH 5.0 OF ESSAA.
INTERMITTENT TIMING PROBLEM FIXED BY CHANGING BAUD RATE TO 9600
FROM 19200 IN ALL TESTS. (TEST 10 THE BAUD RATE TIMING TEST DOES
CHECK THE BAUD RATE AT 19200.)
REMOVE SYSTEM FATAL ERRORS IN INTERRUPT HANDLERS.
ALLOW SCOPE LOOPS ON DEVICE FATAL ERRORS.
MODIFIED BY GARY HUFF DATE 17-APR-1980
VERSION 2.1 MODIFIED TO BE COMPATIBLE WITH ALL VAX
PROCESSORS.
INCLUDE A NOTE STATING THAT ON M7814 (20MA) DZ11
NO RECEIVE INPUT SHOULD EVER BE LEFT UNTERMINATED.
INCLUDE A NOTE IN TEST 19 THAT IF INTERMITTENT
ERRORS ARE OCURRING ON 20MA DZ11 TO BE SURE THAT
THE RECEIVE INPUTS ARE "BLINDED".
ADD $DS_SETIPL #X^17 TO THE BEGINING OF CLEANUP
AND $DS_SETIPL #0 TO THE END OF CLEANUP.
SPEED UP TRANSMIT INTERRUPT HANDLER TO COMPENSATE
FOR SLOWER PROCESSOR SPEEDS ON SOME VAX FAMILY
PROCESSORS.
VERSION 2.2
RE-WROTE TRANSMIT INTERRUPT HANDLER TO COMPENSATE
FOR PECULIARITIES OF SLOWER PROCESSORS. ALSO
FIXED INTERMITTENT BUG IN TEST 19 SUBTEST 1 CAUSED
BY SETTING BREAK BIT WHILE TURNAROUND CONNECTOR
IS PRESENT.
ADD SETTING BREAK BITS IN SECOND PART OF TEST 17.
MODIFIED BY: NICK MCCAMY DATE: 13-MAY-1983
VERSION 3.0
NICK MCCAMY REVISED EVDAA 2.2 TO BECOME 3.0
NICK REWROTE TEST 10 "BAUD RATE TIMING TEST".
THE TEST HAS BEEN SIMPLIFIED AND SHOULD NOT
PRESENT CPU RELATED TIMING PROBLEMS.
NICK ALSO REWROTE TEST 21 SUBTEST 3 "BREAK BIT
TEST". THE TEST HAS BEEN GREATLY SIMPLIFIED
AND THE APPROACH IS DIFFERENT. THE TEST NOW
SETS THE BREAK BIT BEFORE CHARACTERS ARE SENT
OUT. THE TEST USED TO HAVE TIMING PROBLEMS
BECAUSE THE BREAK BIT WAS BEING SET AFTER CHARACTERS
WERE SENT OUT. THE TEST SHOULD NOT PRESENT CPU
RELATED TIMING PROBLEMS.