- ATTACH
The multiport memories to be tested must be attached with the
following command:
DS> ATTACH MA780 SBI MAx y z n p
where:
x - is an arbitrary number from 0 to 7
y - is the TR number of the MA780
z - is the BR (lower) number of the MA780
n - is the MA780 number (from the MA780 front panel)
p - is the Port Number on this CPU
If you are unsure of the parameters of your configuration, type
in any parameters and run the SIZE section to find out the
actual parameters.
- HELP
This program is used to exercise the MA780 memory with
multiple CPUs. There is only one test. This test consists of
an INTERLOCK test, a data read/write test, and a cache
invalidate test. Inter-port interrupts are used to synchronize
CPUs and to create background activity. (Type HELP ESCCB
SEQUENCE).
All MA780 ports that are on-line must have the program
started in them because the first CPU started will be the master
and will wait for all other on-line ports to "come alive".
If more than one MA780 is to be tested, the order of testing
(SELECT order) must be the same on all CPUs otherwise, the
master will not be able to synchronize with all CPUs.
Each pass takes approximately 5 minutes per array board per
multi-port memory per CPU pair to complete. That is, 3 CPUs
with one array board takes 8 minutes and 4 CPUs would take 10
minutes.
- SEQUENCE
One pass consists of the following 9 steps:
1 All CPUs perform interlock test together.
2 Each CPU fills their buffers with compliment of test
pattern.
3 All CPUs write test pattern into their lower buffer
together.
4 Each CPU checks lower buffer for correct data.
5 All CPUs copy lower buffer into their upper buffer
together.
6 Each CPU checks upper buffer for correct data.
7 Repeat steps 2 thru 6 for 44 data patterns.
8 Repeat steps 2 thru 7 for all array boards. (See QUICK
for more info)
9 All CPUs perform cache invalidate test.
- SECTIONS
The program consists of two sections.
- DEFAULT
This section will execute the test.
- SIZE
This section will only execute the SBI Sizer. This section is
usefull to determine the ATTACH parameters of the multi-port
memory.
- DEVICE
- MA780
Device: 11/780 Multi-Port Memory
Link: SBI
Recommended generic: MAn
Additional information:
TR? [decimal 1-15]
BR? [decimal 4 or 6]
MPM? [decimal 0-3]
PORT? [decimal 0-3]
- EVENT
22 When set, inter-port interrupts are inhibited during the
execution of the subroutines that transfer data to the memory
and the routines that fill/compare data buffers.
23 When set, the SBI configuration typeout is inhibited.
- QUICK
If set, the program will only test the first array card. That
is, one pass will only use buffers on the first array card. If
clear, buffers are allocated to all array cards in the memory.
- TRACE
If set, the program will indicate which step of the test
sequence is being performed. (Type HELP ESCCB SEQUENCE). NOTE:
The TRACE flag must be either on or off FOR ALL PROCESSORS.
- SUMMARY
If single bit errors are detected in the ma780 during the test
they are logged. The summary section will typeout the error log
of single bit errors.